Yu-Cheng Wu
I am an incoming graduate student at MIT EECS. I received my B.S.E. from the Dept. of Electrical Engineering at National Taiwan University in June 2023. I am fortunate to have worked with Prof. Chung-Wei Lin on deep-reinforcement-learning(DRL)-based design space exploration for cyber-physical systems complying with Time-Sensitive Networking, Prof. An-Yeu (Andy) Wu on DRL-based energy-accuracy optimization for deep learning inference using Near/In-Memory-Computing hardware accelerators, and Prof. Jie-Hong Roland Jiang on quantized neural network circuit synthesis.
news
| Jun 26, 2024 | Our work, Deep-Reinforcement-Learning-Based Design Space Exploration for Time-Sensitive Networking, was accepted to the 2024 International Symposium on Automated Technology for Verification and Analysis (ATVA)! |
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| Feb 1, 2024 | I was admitted to the Doctoral program at MIT EECS! |
| Sep 7, 2023 | I presented our work, DEA-NIMC: Dynamic Energy-Aware Policy for Near/In-Memory Computing Hybrid Architecture, at the 2023 IEEE System-on-Chip Conference (SOCC), Santa Clara, CA, USA. |
| Jun 23, 2023 | Our work, DEA-NIMC: Dynamic Energy-Aware Policy for Near/In-Memory Computing Hybrid Architecture, was accepted to the 2023 IEEE System-on-Chip Conference (SOCC) for oral presentation! |
| Jun 11, 2023 | I graduated with a B.S.E. from the Dept. of Electrical Engineering at National Taiwan University! |